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Difference between revisions of "DMA Resource"
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Some hardware targets include a DMA engine which can be used for general purpose copying. This article describes the DMA engines available and how to use them. |
Some hardware targets include a DMA engine which can be used for general purpose copying. This article describes the DMA engines available and how to use them. |
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| − | == |
+ | == Hardware Features == |
The Direct Memory Access (DMA) Engines found in the NXP/Freescale p5020, p5040 and p1022 System On a Chip (SoC)s, found in the AmigaONE X5000/20, X5000/40 and A1222 respectively, are quite flexible and powerful. Each of these chips contains two distinct engines with four data channels each. This provides the ability to have a total of eight DMA Channels working at once, with up to two DMA transactions actually being executed at the same time (one on each of the two DMA Engines). |
The Direct Memory Access (DMA) Engines found in the NXP/Freescale p5020, p5040 and p1022 System On a Chip (SoC)s, found in the AmigaONE X5000/20, X5000/40 and A1222 respectively, are quite flexible and powerful. Each of these chips contains two distinct engines with four data channels each. This provides the ability to have a total of eight DMA Channels working at once, with up to two DMA transactions actually being executed at the same time (one on each of the two DMA Engines). |
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| − | Further, each of the four DMA Channels found in a DMA Engine may be individually programmed to handle either; a single transaction, a ''Chain'' of transactions, or even ''Lists'' of ''Chains'' of transactions. The DMA Engines automatically arbitrate between each DMA Channel following programmed bandwidth settings for each Channel (typically 1024 bytes) |
+ | Further, each of the four DMA Channels found in a DMA Engine may be individually programmed to handle either; a single transaction, a ''Chain'' of transactions, or even ''Lists'' of ''Chains'' of transactions. The DMA Engines automatically arbitrate between each DMA Channel following programmed bandwidth settings for each Channel (typically 1024 bytes). |
| + | |||
| + | This means that after completing a transfer of 1024 bytes (for example), the hardware will consider switching to the next Channel to allow it to move another block of data, and so on in a round-robin fashion. If all other DMA Channels on a given DMA Engine are idle when arbitration would take place, the hardware will not arbitrate and simply continue processing the transaction(s) for the Channel it is on. |
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Revision as of 22:49, 12 November 2019
DMA Engine
Some hardware targets include a DMA engine which can be used for general purpose copying. This article describes the DMA engines available and how to use them.
Hardware Features
The Direct Memory Access (DMA) Engines found in the NXP/Freescale p5020, p5040 and p1022 System On a Chip (SoC)s, found in the AmigaONE X5000/20, X5000/40 and A1222 respectively, are quite flexible and powerful. Each of these chips contains two distinct engines with four data channels each. This provides the ability to have a total of eight DMA Channels working at once, with up to two DMA transactions actually being executed at the same time (one on each of the two DMA Engines).
Further, each of the four DMA Channels found in a DMA Engine may be individually programmed to handle either; a single transaction, a Chain of transactions, or even Lists of Chains of transactions. The DMA Engines automatically arbitrate between each DMA Channel following programmed bandwidth settings for each Channel (typically 1024 bytes).
This means that after completing a transfer of 1024 bytes (for example), the hardware will consider switching to the next Channel to allow it to move another block of data, and so on in a round-robin fashion. If all other DMA Channels on a given DMA Engine are idle when arbitration would take place, the hardware will not arbitrate and simply continue processing the transaction(s) for the Channel it is on.
